The Perfect Storm – 10nm and 7nm FinFET Power Integrity
- Cells have exponentially higher di/dt
- There is significantly higher on-chip power density at 10nm and 7nm
- Wires don’t scale at the same pace as cells
- The via/sheet resistance has increased
- Strict uni-directional routing is now mandatory
The consequences are sizeable:
- The high Dynamic Voltage Drop (DVD) requires an excessive PDN
- An excessive PDN means low routability
- Low routability cause timing/size closure problems and low utilization
- Lower utilization = die size increase = lower profit
Customer trials on 7nm physical implementation are yielding the lowest utilization seen in a very long time, and this is independent of which brand of Place and Route tools being used.
While the physics of the process can’t be changed, the Physical Design and implementation can be significantly improved using FloorDirector to optimize the SoC’s Power Integrity before clock tree synthesis: FloorDirectors optimized intelligent CTS directives significantly reduces the designs simultaneous switching, making it possible to reduce the DVD across the full block.
This reduced Bulk-DVD significantly relaxes the PDN requirements in the SoC floorplanning phase, thereby using less metal for the PDN and leaving more for routing.
Best-in-class Power Integrity at 10nm and 7nm is required to increase utilization, timing closure and profit.