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SCREAMER – A Demonstrator Chip for Spectral Noise Optimization By Clock Latency Scheduling

While we normally focus on SoC Power Integrity, the rise of Internet-of-Things (IoT) makes it highly relevant to share some silicon measurement results with the RF and Mixed Signal design community. Normally, power integrity (PI) is looked at in the time domain, but in this work we looked at it from a frequency spectrum perspective. Silicon measurements prove how shaping the dynamic current demand waveform, and thereby changing the noise spectrum, can significantly improve the operating conditions for RF circuits on-chip.

This abstract outlines the design and actual measurement of a 130 nm test chip named SCREAMER for reducing the digital switching noise in synchronous circuits, and uses clock latency scheduling as a means to reduce switching noise in the frequency domain.

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