FloorDirector is a physical implementation tool with capabilities in timing, peak current demand and Dynamic Voltage Drop ( DVD ) optimization. It utilizes full MCMM operation and offers design flow integration with all major EDA backend flows.

 

Multi-Corner-Multi-Mode

FloorDirector provides MCMM and Multi-Use-Case operation in all process technologies and high-speed designs, multi-mode capabilities. You can specify as many corners and scenarios as required to be considered during optimizations.

 

Multiple Targets, Corners and Use-Cases

In addition to support of Multi-Mode/Corner/Use-Case, FloorDirector allow designers to apply concurrent optimization targets to all key metrics  across all modes, corners and use-cases. A backend designer can, for example, choose to target optimization of peak current demand in Test Mode using vectorless, while simultaneously optimizing a specific functional mode using a full or partial VCD . FloorDirector will optimize using all use-cases and scenarios, and determine one single solution for one common clock tree implementation which will meet this complex balance of constraints in all modes of operation.

The optimization process is non-intrusive (no changes to the original design database), which makes it adaptable to all existing EDA flows.

Files needed for an optimization are SDC, SDF, Verilog gate-level netlist, LEF, DEF. VCD files are optional, FloorDirector supports vectorless operation too.
The analysis and optimization will generate a set of Clock Tree Synthesis directives, which drive CTS tools to implement a clock tree with precisely scheduled latency offsets. This will reduce the peak current and power noise as desired, without generate a clock tree overhead or introduce timing violations.

 

Static Timing Analysis

FloorDirector complies with advanced timing requirements; either from the SDC’s or set up in FloorDirector directly. FloorDirector makes use of a  natively implemented STA engine, and MCMM timing will be honored during each of the optimization phases, and meeting the constraints (or relaxations) the designer instructs.

Proven with Mainstream CTS Solutions

Since 2008, Teklatech has been working actively with other EDA suppliers to ensure our solution’s compliance with mainstream CTS solutions from Cadence®, Synopsys®, Magma®, AtopTech®, Mentor Graphics®, including the latest concurrent clock- and datapath-optimizing CTS solutions, such as CC-Opt or ICC2-CCD.

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