The FloorDirector platform expands into timing optimization

The release of FloorDirector® 5.0 marks a new milestone for Teklatech with the expansion of the platform into timing optimization. The new optimization capabilities within Bulk Timing Optimization will be available as a new stand-alone tool: TimingOptimizer™. The tool...

Teklatech on garysmithEDA’s “What to See at DAC 2017”

Teklatech makes the GarySmithEDA shortlist of “What to See at DAC 2017”   It’s a great start on a Friday morning to see that Teklatech – out of 148 exhibiting companies – has been shortlisted by the leading EDA industry analyst GarySmithEDA as...

H.O.T. Party @ DAC2017 – Message from Jim Hogan

H.O.T. Party @ DAC2017 ! Dear EDA Colleagues, With a little help from Teklatech, my favorite Danes and one of our sponsors that makes this party possible, I wanted to reach out and tell you that we have a GREAT PARTY lined up for you again this year. It’s the...

Timing and Power Integrity Closure on 10nm & 7nm

We are just a few days away from DAC, and since last year’s DAC we have been working with our FloorDirector customers to reduce bulk-DVD significantly and improve design closure on 10nm and the first 7nm designs. As you know, reducing bulk-DVD reduces DVD levels...

Power Integrity @ DAC2017

Power Integrity @ DAC2017 Another year have (almost) passed, and we can start seeing DAC 2017 in the horizon. We have had an exciting year solving power integrity on 10nm and 7nm, it is indeed ‘The Perfect Storm‘ and proving to be a major challenge for all...

10nm And 7nm Routability – How Is Your CAD Flow Doing?

At DesignCon in January, I was a panelist at a panel session entitled “Power Integrity For 10nm/7nm SoCs – Overcoming Physical Design Challenges And TAT.” I was on the panel together with Arvind Vel, Sr. Director Applications Engineering, ANSYS, Inc. and Ruggero...

Power Integrity @ DesignCon 2017

If you are working with power integrity in physical design and approaching the 10nm and 7nm process nodes, you should not miss DesignCon this year. The DesignCon committee has set up a conference track titled “Overcoming Chip & Package Challenges in Signal/Power...

Challenges at 10nm and 7nm – Teklatech in the News

Focus and attention to on-chip power integrity is accelerating as more and more companies move towards 10nm and 7nm. Semiconductor Engineering have been running a series of articles on the challenges at those nodes with participation from Krishna Balachandran,...

Dynamic Peak Power As A Proxy For DVD? Really?

Optimizing for dynamic voltage drop at the beginning of physical implementation. DECEMBER 8TH, 2016 – BY: TOBIAS BJERREGAARD Dynamic-voltage-drop (DVD) concerns have grown substantially at the 10nm and 7nm silicon process nodes. DVD refers to the transient...

Teklatech – In the News

Teklatech is in the news again, serial-entrepreneur and investor Jim Hogan explains his view on investment strategies and companies that has caught his attention: “I have a company in Denmark called Teklatech. They did some non-intuitive stuff. They figured out...