SoC Power Integrity – A key challenge

During the past decade, power integrity (PI) sign-off analysis solutions have become an integral part of most – if not all – backend physical design flows. Especially at process nodes below 16nm, the dynamic power and rail analysis sign-off methodology is a must-have in the physical backend flow.
While that’s all fine, there is a major problem with a sign-off analysis tool: It only analyzes the design and identifies there is a problem. It doesn’t come up with a proper solution to the problem.

Improving on-chip DVD using FloorDirector

Improving on-chip DVD using FloorDirector

FloorDirector is different and unique: It’s an optimization tool which can reduce DVD (both peak and bulk DVD) as well as in-rush current before physical implementation, and thereby remove problems and create sufficient margin for an optimal implementation. And, you don’t have to see the sign-off analysis before running a FloorDirector optimization, but you can optimize as a systematic part of your EDA flow just before Clock Tree Synthesis. This will give you a better product by design, and save you significant engineering time and design closure iterations. FloorDirector is a unique EDA tool, and Teklatech is the only company in the EDA industry offering a solution aimed at this essential problem.

Mobile SoC

When Mobile System-on-Chip designs reached 20nm, they passed a threshold on a number of exponentially challenging points. It became a turning point for many customer designs with a through-the-roof silicon power density, the process di/dt demanding more metal for power routing, while the cell density caused routing congestion and thereby required more metal for routing. Effectively, such conflicting demands will increase the die size, and prohibit that you get the optimal die size from a given process. Using FloorDirector will allow you to keep the cell density without starvation, while still having a routable design.

For Mobile SoC, FloorDirector has in the past been used successfully on 40, 28nm and 20nm. FloorDirector is currently being used on 10nm FinFET next-gen Mobile SoC production, as well as 7nm trials.

Network Switching SoC

The huge Network Switching SoC’s share some of the DVD challenges of the mobile SoC’s, but are additionally challenged by in-rush current; the instantaneous demand for hundreds of Ampere’s onto the chip is limited by the on-chip Power Delivery Network, the package technology and the cost/size of external power supply. Using FloorDirector will reduce the peak current demand and smoothen the slope of the current demand, allowing you to meet your system’s power integrity metrics.

FloorDirector is currently being applied on 16nm FinFET next-gen Network Switching SoC’s.

Internet-Of-Things (IoT) Devices

Interestingly, small designs are pushed to the edge, too. Even though they are designed on a slower/older process, they will be constrained in other dimensions; they will use cheap packages, fewer metal layers, weaker power supplies, sub-optimal RF antenna’s etc; all the important pieces to solve the profitability puzzle. Optimizing your design can allow for lower DVD and smoother in-rush current will allow lower supply voltages and longer battery run time, smaller off-chip and on-chip regulators.
RF improvements are highly interesting too, but a slightly different discussion: Looking at on-chip power integrity, we are operating in the time domain. However, for RF it’s possible look at the pulses in the frequency domain and analyze the effect of an optimization. Teklatech have silicon measurements showing a massive improvement in the frequency noise spectrum after a FloorDirector optimization, thereby allowing for a more optimal low-cost implementation of small RF systems.

FloorDirector is currently being applied on 40nm, 28nm and beyond for various IoT designs, as well as more traditional RF and processor systems.


Learn more about the Power Integrity challenges at 10nm and 7nm process nodes

10nm And 7nm Routability – How Is Your CAD Flow Doing?

At DesignCon in January, I was a panelist at a panel session entitled “Power Integrity For 10nm/7nm SoCs – Overcoming Physical Design Challenges And TAT.” I was on the panel together with Arvind Vel, Sr. Director Applications Engineering, ANSYS, Inc. and Ruggero...

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Dynamic Peak Power As A Proxy For DVD? Really?

Optimizing for dynamic voltage drop at the beginning of physical implementation. DECEMBER 8TH, 2016 - BY: TOBIAS BJERREGAARD Dynamic-voltage-drop (DVD) concerns have grown substantially at the 10nm and 7nm silicon process nodes. DVD refers to the transient voltage...

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Hitting The Power Integrity Wall At 10nm

Power integrity challenges stand in the way of exploiting the benefits of scaling. SEPTEMBER 8TH, 2016 - BY: TOBIAS BJERREGAARD At 10nm and beyond, the breakdown of some historic trends tied to Moore’s Law is making it harder to fully harvest the benefits of scaling...

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