Power Integrity @ DAC2017
Another year have (almost) passed, and we can start seeing DAC 2017 in the horizon. We have had an exciting year solving power integrity on 10nm and 7nm, it is indeed ‘The Perfect Storm‘ and proving to be a major challenge for all customers moving into 7nm.

Lets talk at DAC! Set a time to meet with Teklatech’s CEO Tobias Bjerregaard and our technical staff. You can reach us on DAC2017@teklatech.com, we hope to see you there and discuss how FloorDirector can improve power integrity, routability and timing in your backend flow.

10nm and 7nm Power Integrity
Tobias Bjerregaard, CEO of Teklatech, participated a panel discussion on DesignCon in January on the track titled “Overcoming Chip & Package Challenges in Signal/Power Integrity”, and he wrote “One of the most eye-opening moments was when Arvind Vel got a question from the audience: “Looking at the transition to 10nm and 7nm; from your customer interaction, what are yours and ANSYS’ experiences on the biggest surprise that customers see when arriving to those process nodes?” Arvinds answer was not DVD, EMI or thermal..! You can read the blog here.

Managing Voltage Drop At 10/7nm
In case you haven’t read it yet, Ann Steffora Mutschler published an article on “Building a power delivery network with the low implementation overhead becomes more problematic at advanced nodes” with inputs from ARM, Ansys, Teklatech, Cadence and Mentor. It’s a worthwhile read for sure, you can find the article here.