DesignCon 2017

If you are working with power integrity in physical design and approaching the 10nm and 7nm process nodes, you should not miss DesignCon this year. The DesignCon committee has set up a conference track titled “Overcoming Chip & Package Challenges in Signal/Power Integrity”:

On Wednesday, Feb 1 3:00pm – 4:15pm, Teklatech, Ansys/Apache and Broadcom will have a panel discussion titled “Power Integrity for 10nm/7nm SoC’s – Overcoming Physical Design Challenges and TAT”. 

We will be discussing and sharing experiences from a PI optimization/reduction, PI analysis/signoff and end-customer perspective: “Abstract: SoC Power Integrity is a major challenge moving towards 10 and 7nm, and a new implementation and sign-off approach is needed to keep harvesting the benefits of technology scaling. Power Integrity is a multi-faceted problem which needs to be tackled smarter and more effectively at different steps in the flow. It will require design teams moving away from conventional wisdom towards a simulation aware implementation and signoff practices. Takeaway: Understanding on power integrity challenges on 14/10/7nm, and considerations to make before the first trial run.”

You can reach Teklatech’s CEO at if would like to have a separate discussion before or after the session.

We hope to see you there!

You can read Teklatech’s latest commentaries on 10nm and 7nm Power Integrity here and here.

You can read the details on the Power Integrity Track here.