The FloorDirector® Platform

FloorDirector® is an ASIC/SoC backend platform to analyze and optimize dynamic power integrity and timing.

At advanced process nodes, power integrity has a direct impact on area utilization, timing, as well as fabrication yield. Power integrity closure puts high demand on resources used in implementing the power delivery network. This leads to a routability crunch, making it hard to achieve the targeted area utilization. Timing closure is also impacted, both in terms of setup-time, as well as hold-time.

Optimal design closure at 10nm and 7nm nodes thus requires specialized approaches beyond what is available in standard Place&Route tools. The FloorDirector platform provides capabilities to take SoC design one step beyond standard.

FloorDirector implements a holistic and placement-aware view of dynamic power, power grid architecture, dynamic voltage drop, MMMC timing and clock architecture, enabling a range of tools for power integrity and timing optimization.

FloorDirector-PWR: Optimizes dynamic power integrity at the pre-CTS stage. Dynamic Voltage Drop (DVD) is reduced, allowing a smaller power grid to be used, thus maintaining power integrity margin with better routability.

FloorDirector-BTO: Optimizes bulk timing at the pre-CTS stage, to create a better starting point for the physical backend. This leads to reduced postRoute setup- and hold-TNS and easier design closure.

FloorDirector-DVD: Analyzes Dynamic Voltage drop at pre- or post-CTS design stages. Allows fast, truly iterative what-if analysis, to arrive at the most optimal power grid implementation, with the smallest impact on routability.

FloorDirector interfaces to existing design flows through standard design and library formats.


FloorDirector is a platform for optimizing SoC dynamic power integrity and timing early in the design flow. 


The FloorDirector platform is silicon-proven down to 7nm


Power Integrity Optimization


Reducing the SoC’s dynamic voltage drop (DVD), without penalties such as violated timing paths or a large overhead in clock tree buffers, allows a smaller power grid and better routability.

Bulk Timing Optimization


Reducing total negative slack (TNS) and number of failing endpoints (NFEs) at an early design stage, creates a better starting point for the physical backend, resulting in lower ECO overhead and easier design closure.

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