We are just a few days away from DAC, and since last year’s DAC we have been working with our FloorDirector customers to reduce bulk-DVD significantly and improve design closure on 10nm and the first 7nm designs. As you know, reducing bulk-DVD reduces DVD levels across the full block, and allows sparser PDNs and releases routing channels which is highly critical for design closure on these nodes.

Now, after 5 months of trials with the leading customers, we are expanding FloorDirector’s use-models into timing optimization! FloorDirector’s methodology is unique as it optimizes bulk-timing, meaning reducing the Number of Failing Endpoints (NFE) as well as reducing Total Negative Slack (TNS), for the full block all at once. As FloorDirector’s optimization methodology takes a top-down-full-design optimization approach, it is fully complementary to CC-Opt’s and ICC2-CCD’s bottom-up-path-by-path approach.

 

The example below (10nmFF) shows the design before and after a FloorDirector bulk-timing optimization: The number of failing endpoints are reduced by more than 50%, and near-critical endpoints have an equally high improvement! Bulk-timing optimizations improves timing across the full design, making remaining design closure and ECO’s complete in record time.

 

 

 

 

But there is much more to talk about than this, so stop by booth #441 and let us share our experiences with you on power integrity and timing optimizations on 10nm and 7nm designs.

Or, even better: Email us to set a meeting time at DAC2017@teklatech.com

See you there!